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<div id="catalog">
<ul>
<li><a href="#Message" style=" font-size: 16px;">PnR Messages</a></li>
<!--<li><a href="#Summary" style=" font-size: 16px;">PnR Summaries</a></li>-->
<li><a href="#PnR_Details" style=" font-size: 16px;">PnR Details</a>
<li><a href="#Resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#Resource_Usage_Summary" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#I/O_Bank_Usage_Summary" style=" font-size: 14px;">I/O Bank Usage Summary</a></li>
<li><a href="#Global_Clock_Usage_Summary" style=" font-size: 14px;">Global Clock Usage Summary</a></li>
<li><a href="#Global_Clock_Signals" style=" font-size: 14px;">Global Clock Signals</a></li>
<li><a href="#Pinout_by_Port_Name" style=" font-size: 14px;">Pinout by Port Name</a></li>
<li><a href="#All_Package_Pins" style=" font-size: 14px;">All Package Pins</a></li>
</ul>
</li>
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<div id="content">
<h1><a name="Message">PnR Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Gowin PnR Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Users\hankg\OneDrive\Works\Gowin\Cortex-M3-DualCam\impl\gwsynthesis\gowin_empu_m3.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>C:\Users\hankg\OneDrive\Works\Gowin\Cortex-M3-DualCam\src\dual_5640.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">GOWIN Version</td>
<td>V1.9.8</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV55PG484C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-55C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Mon Nov 29 13:27:58 2021
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="PnR_Details">PnR Details</a></h1>
<!--<h1><a name="Summary">PnR Summaries</a></h1>-->
<table class="summary_table">
<tr>
<td class="label">Place & Route Process</td>
<td>Running placement:
   Placement Phase 0: CPU time = 0h 0m 19s, Elapsed time = 0h 0m 19s
   Placement Phase 1: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
   Placement Phase 2: CPU time = 0h 1m 28s, Elapsed time = 0h 1m 28s
   Placement Phase 3: CPU time = 0h 0m 40s, Elapsed time = 0h 0m 40s
   Total Placement: CPU time = 0h 2m 29s, Elapsed time = 0h 2m 29s
Running routing:
   Routing Phase 0: CPU time = 0h 0m 0.026s, Elapsed time = 0h 0m 0.026s
   Routing Phase 1: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
   Routing Phase 2: CPU time = 0h 2m 59s, Elapsed time = 0h 2m 59s
   Total Routing: CPU time = 0h 3m 2s, Elapsed time = 0h 3m 2s
Generate output files:
   CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s
</td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 5m 44s, Elapsed time = 0h 5m 44s, Peak memory usage = 1015MB</td>
</tr>
</table>
<br/>
<h1><a name="Resource">Resource</a></h1>
<!--<h1><a name="Summary">PnR Summaries</a></h1>-->
<h2><a name="Resource_Usage_Summary">Resource Usage Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>32749/54720</td>
<td>59%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --LUT,ALU,ROM16</td>
<td>28867(27115 LUT, 1752 ALU, 0 ROM16)</td>
<td>-</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --SSRAM(RAM16)</td>
<td>647</td>
<td>-</td>
</tr>
<tr>
<td class="label">Register</td>
<td>7627/41997</td>
<td>18%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --Logic Register as Latch</td>
<td>1/41040</td>
<td>1%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --Logic Register as FF</td>
<td>7603/41040</td>
<td>18%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --I/O Register as Latch</td>
<td>0/957</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --I/O Register as FF</td>
<td>23/957</td>
<td>2%</td>
</tr>
<tr>
<td class="label">CLS</td>
<td>19935/27360</td>
<td>72%</td>
</tr>
<tr>
<td class="label">I/O Port</td>
<td>99</td>
<td>-</td>
</tr>
<tr>
<td class="label">I/O Buf</td>
<td>89</td>
<td>-</td>
</tr>
<tr>
<td class="label"> &nbsp &nbsp --Input Buf</td>
<td>29</td>
<td>-</td>
</tr>
<tr>
<td class="label"> &nbsp &nbsp --Output Buf</td>
<td>38</td>
<td>-</td>
</tr>
<tr>
<td class="label"> &nbsp &nbsp --Inout Buf</td>
<td>22</td>
<td>-</td>
</tr>
<tr>
<td class="label">IOLOGIC</td>
<td>16 IDES8_MEM<br/>24 OSER8<br/>20 OSER8_MEM<br/>4 OSER10<br/>40 IODELAY<br/></td>
<td>40%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>32 SP<br/>33 SDPB<br/>15 SDPX9B<br/>2 pROM<br/></td>
<td>58%</td>
</tr>
<tr>
<td class="label">DSP</td>
<td>1 MULT36X36<br/></td><td>10%</td>
</tr>
<tr>
<td class="label">PLL</td>
<td>4/6</td>
<td>66%</td>
</tr>
<tr>
<td class="label">DCS</td>
<td>0/8</td>
<td>0%</td>
</tr>
<tr>
<td class="label">DQCE</td>
<td>0/24</td>
<td>0%</td>
</tr>
<tr>
<td class="label">OSC</td>
<td>0/1</td>
<td>0%</td>
</tr>
<tr>
<td class="label">CLKDIV</td>
<td>2/8</td>
<td>25%</td>
</tr>
<tr>
<td class="label">DLLDLY</td>
<td>0/8</td>
<td>0%</td>
</tr>
<tr>
<td class="label">DQS</td>
<td>2/22</td>
<td>9%</td>
</tr>
<tr>
<td class="label">DHCEN</td>
<td>1/16</td>
<td>6%</td>
</tr>
</table>
<h2><a name="I/O_Bank_Usage_Summary">I/O Bank Usage Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>I/O Bank</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label">bank 0</td>
<td>4/40(10%)</td>
</tr>
<tr>
<td class="label">bank 1</td>
<td>0/40(0%)</td>
</tr>
<tr>
<td class="label">bank 2</td>
<td>12/46(26%)</td>
</tr>
<tr>
<td class="label">bank 3</td>
<td>5/34(14%)</td>
</tr>
<tr>
<td class="label">bank 4</td>
<td>19/40(47%)</td>
</tr>
<tr>
<td class="label">bank 5</td>
<td>9/40(22%)</td>
</tr>
<tr>
<td class="label">bank 6</td>
<td>17/34(50%)</td>
</tr>
<tr>
<td class="label">bank 7</td>
<td>23/46(50%)</td>
</tr>
</table>
<br/>
<h2><a name="Global_Clock_Usage_Summary">Global Clock Usage Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Global Clock</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label">PRIMARY</td>
<td>8/8(100%)</td>
</tr>
<tr>
<td class="label">SECONDARY</td>
<td>8/8(100%)</td>
</tr>
<tr>
<td class="label">GCLK_PIN</td>
<td>4/8(50%)</td>
</tr>
<tr>
<td class="label">PLL</td>
<td>4/6(66%)</td>
</tr>
<tr>
<td class="label">CLKDIV</td>
<td>2/8(25%)</td>
</tr>
<tr>
<td class="label">DLLDLY</td>
<td>0/8(0%)</td>
</tr>
</table>
<br/>
<h2><a name="Global_Clock_Signals">Global Clock Signals:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Signal</b></td>
<td><b>Global Clock</b></td>
<td><b>Location</b></td>
</tr>
<tr>
<td class="label">cam1_pclk_d</td>
<td>PRIMARY</td>
<td> TR TL BR BL</td>
</tr>
<tr>
<td class="label">MCU_SYS_CLK</td>
<td>PRIMARY</td>
<td> TR TL BR BL</td>
</tr>
<tr>
<td class="label">n344_6</td>
<td>PRIMARY</td>
<td> BR</td>
</tr>
<tr>
<td class="label">clk_100m</td>
<td>PRIMARY</td>
<td> TL BL</td>
</tr>
<tr>
<td class="label">dma_clk</td>
<td>PRIMARY</td>
<td> TR TL BR BL</td>
</tr>
<tr>
<td class="label">pix_clk</td>
<td>PRIMARY</td>
<td> TR TL BL</td>
</tr>
<tr>
<td class="label">dri_clk_2</td>
<td>PRIMARY</td>
<td> BL</td>
</tr>
<tr>
<td class="label">dri_clk_2</td>
<td>PRIMARY</td>
<td> TL BL</td>
</tr>
<tr>
<td class="label">sys_clk_d</td>
<td>SECONDARY</td>
<td> -</td>
</tr>
<tr>
<td class="label">cam0_pclk_d</td>
<td>SECONDARY</td>
<td> -</td>
</tr>
<tr>
<td class="label">cam0_vsync_d</td>
<td>SECONDARY</td>
<td> -</td>
</tr>
<tr>
<td class="label">JTAG_9_1</td>
<td>SECONDARY</td>
<td> -</td>
</tr>
<tr>
<td class="label">sysRstGen_3</td>
<td>SECONDARY</td>
<td> -</td>
</tr>
<tr>
<td class="label">poreset_n_qq</td>
<td>SECONDARY</td>
<td> -</td>
</tr>
<tr>
<td class="label">hdmi4_rst_n</td>
<td>SECONDARY</td>
<td> -</td>
</tr>
<tr>
<td class="label">ddr_rst</td>
<td>SECONDARY</td>
<td> -</td>
</tr>
<tr>
<td class="label">clk_ddr_200MHz</td>
<td>HCLK</td>
<td>LEFT[0] RIGHT[0]</td>
</tr>
<tr>
<td class="label">serial_clk</td>
<td>HCLK</td>
<td>TOP[0]</td>
</tr>
</table>
<br/>
<h2><a name="Pinout_by_Port_Name">Pinout by Port Name:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Port Name</b></td>
<td><b>Diff Pair</b></td>
<td><b>Loc./Bank</b></td>
<td><b>Constraint</b></td>
<td><b>Dir.</b></td>
<td><b>Site</b></td>
<td><b>IO Type</b></td>
<td><b>Drive</b></td>
<td><b>Pull Mode</b></td>
<td><b>PCI Clamp</b></td>
<td><b>Hysteresis</b></td>
<td><b>Open Drain</b></td>
<td><b>Slew Rate</b></td>
<td><b>Vref</b></td>
<td><b>Single Resistor</b></td>
<td><b>Diff Resistor</b></td>
<td><b>BankVccio</b></td>
</tr>
<tr>
<td class="label">sys_clk</td>
<td></td>
<td>M19/2</td>
<td>Y</td>
<td>in</td>
<td>IOR44[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">sys_rst_n</td>
<td></td>
<td>AB3/5</td>
<td>Y</td>
<td>in</td>
<td>IOB21[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">UART0RXD_i</td>
<td></td>
<td>L20/2</td>
<td>Y</td>
<td>in</td>
<td>IOR35[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam0_pclk</td>
<td></td>
<td>W14/4</td>
<td>Y</td>
<td>in</td>
<td>IOB73[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam0_vsync</td>
<td></td>
<td>W12/4</td>
<td>Y</td>
<td>in</td>
<td>IOB52[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam0_href</td>
<td></td>
<td>W13/4</td>
<td>Y</td>
<td>in</td>
<td>IOB52[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam0_data[0]</td>
<td></td>
<td>W15/4</td>
<td>Y</td>
<td>in</td>
<td>IOB73[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam0_data[1]</td>
<td></td>
<td>Y17/4</td>
<td>Y</td>
<td>in</td>
<td>IOB72[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam0_data[2]</td>
<td></td>
<td>AA17/4</td>
<td>Y</td>
<td>in</td>
<td>IOB72[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam0_data[3]</td>
<td></td>
<td>Y19/4</td>
<td>Y</td>
<td>in</td>
<td>IOB84[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam0_data[4]</td>
<td></td>
<td>W16/4</td>
<td>Y</td>
<td>in</td>
<td>IOB76[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam0_data[5]</td>
<td></td>
<td>Y15/4</td>
<td>Y</td>
<td>in</td>
<td>IOB63[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam0_data[6]</td>
<td></td>
<td>AA20/4</td>
<td>Y</td>
<td>in</td>
<td>IOB89[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam0_data[7]</td>
<td></td>
<td>Y20/4</td>
<td>Y</td>
<td>in</td>
<td>IOB89[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam1_pclk</td>
<td></td>
<td>W19/4</td>
<td>Y</td>
<td>in</td>
<td>IOB91[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam1_vsync</td>
<td></td>
<td>V19/4</td>
<td>Y</td>
<td>in</td>
<td>IOB91[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam1_href</td>
<td></td>
<td>H22/2</td>
<td>Y</td>
<td>in</td>
<td>IOR32[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam1_data[0]</td>
<td></td>
<td>G22/2</td>
<td>Y</td>
<td>in</td>
<td>IOR29[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam1_data[1]</td>
<td></td>
<td>V15/4</td>
<td>Y</td>
<td>in</td>
<td>IOB68[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam1_data[2]</td>
<td></td>
<td>U16/4</td>
<td>Y</td>
<td>in</td>
<td>IOB86[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam1_data[3]</td>
<td></td>
<td>V16/4</td>
<td>Y</td>
<td>in</td>
<td>IOB86[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam1_data[4]</td>
<td></td>
<td>E22/2</td>
<td>Y</td>
<td>in</td>
<td>IOR28[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam1_data[5]</td>
<td></td>
<td>G21/2</td>
<td>Y</td>
<td>in</td>
<td>IOR29[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam1_data[6]</td>
<td></td>
<td>J22/2</td>
<td>Y</td>
<td>in</td>
<td>IOR32[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam1_data[7]</td>
<td></td>
<td>D22/2</td>
<td>Y</td>
<td>in</td>
<td>IOR18[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">UART0TXD_o</td>
<td></td>
<td>K20/2</td>
<td>Y</td>
<td>out</td>
<td>IOR35[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam0_rst_n</td>
<td></td>
<td>L19/2</td>
<td>Y</td>
<td>out</td>
<td>IOR34[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam0_scl</td>
<td></td>
<td>Y18/4</td>
<td>Y</td>
<td>out</td>
<td>IOB84[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam1_rst_n</td>
<td></td>
<td>V14/4</td>
<td>Y</td>
<td>out</td>
<td>IOB68[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam1_scl</td>
<td></td>
<td>F22/2</td>
<td>Y</td>
<td>out</td>
<td>IOR28[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">O_tmds_clk_p</td>
<td>O_tmds_clk_n</td>
<td>A2,A3/0</td>
<td>Y</td>
<td>out</td>
<td>IOT18</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">O_tmds_data_p[0]</td>
<td>O_tmds_data_n[0]</td>
<td>B6,A6/0</td>
<td>Y</td>
<td>out</td>
<td>IOT24</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">O_tmds_data_p[1]</td>
<td>O_tmds_data_n[1]</td>
<td>A9,A10/0</td>
<td>Y</td>
<td>out</td>
<td>IOT40</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">O_tmds_data_p[2]</td>
<td>O_tmds_data_n[2]</td>
<td>A11,A12/0</td>
<td>Y</td>
<td>out</td>
<td>IOT42</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<tr>
<td class="label">O_ddr_addr[0]</td>
<td></td>
<td>F1/7</td>
<td>Y</td>
<td>out</td>
<td>IOL20[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_addr[1]</td>
<td></td>
<td>V5/6</td>
<td>Y</td>
<td>out</td>
<td>IOL82[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_addr[2]</td>
<td></td>
<td>G6/7</td>
<td>Y</td>
<td>out</td>
<td>IOL5[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_addr[3]</td>
<td></td>
<td>E5/7</td>
<td>Y</td>
<td>out</td>
<td>IOL2[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_addr[4]</td>
<td></td>
<td>V3/6</td>
<td>Y</td>
<td>out</td>
<td>IOL73[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_addr[5]</td>
<td></td>
<td>F2/7</td>
<td>Y</td>
<td>out</td>
<td>IOL18[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_addr[6]</td>
<td></td>
<td>Y22/3</td>
<td>Y</td>
<td>out</td>
<td>IOR73[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_addr[7]</td>
<td></td>
<td>H5/7</td>
<td>Y</td>
<td>out</td>
<td>IOL14[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_addr[8]</td>
<td></td>
<td>AB22/3</td>
<td>Y</td>
<td>out</td>
<td>IOR79[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_addr[9]</td>
<td></td>
<td>H4/7</td>
<td>Y</td>
<td>out</td>
<td>IOL21[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_addr[10]</td>
<td></td>
<td>P5/6</td>
<td>Y</td>
<td>out</td>
<td>IOL76[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_addr[11]</td>
<td></td>
<td>Y21/3</td>
<td>Y</td>
<td>out</td>
<td>IOR76[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_addr[12]</td>
<td></td>
<td>T5/6</td>
<td>Y</td>
<td>out</td>
<td>IOL83[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_addr[13]</td>
<td></td>
<td>AA1/6</td>
<td>Y</td>
<td>out</td>
<td>IOL74[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_ba[0]</td>
<td></td>
<td>F4/7</td>
<td>Y</td>
<td>out</td>
<td>IOL9[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_ba[1]</td>
<td></td>
<td>T4/6</td>
<td>Y</td>
<td>out</td>
<td>IOL77[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_ba[2]</td>
<td></td>
<td>F3/7</td>
<td>Y</td>
<td>out</td>
<td>IOL11[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_cs_n</td>
<td></td>
<td>W20/3</td>
<td>N</td>
<td>out</td>
<td>IOR77[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_ras_n</td>
<td></td>
<td>D1/7</td>
<td>Y</td>
<td>out</td>
<td>IOL16[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_cas_n</td>
<td></td>
<td>D3/7</td>
<td>Y</td>
<td>out</td>
<td>IOL7[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_we_n</td>
<td></td>
<td>C2/7</td>
<td>Y</td>
<td>out</td>
<td>IOL15[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_clk</td>
<td>O_ddr_clk_n</td>
<td>P22,R22/3</td>
<td>Y</td>
<td>out</td>
<td>IOR46</td>
<td>SSTL15D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_cke</td>
<td></td>
<td>E4/7</td>
<td>Y</td>
<td>out</td>
<td>IOL8[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_odt</td>
<td></td>
<td>B3/7</td>
<td>Y</td>
<td>out</td>
<td>IOL3[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_reset_n</td>
<td></td>
<td>V4/6</td>
<td>Y</td>
<td>out</td>
<td>IOL79[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_dqm[0]</td>
<td></td>
<td>P3/6</td>
<td>Y</td>
<td>out</td>
<td>IOL52[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">O_ddr_dqm[1]</td>
<td></td>
<td>K4/7</td>
<td>Y</td>
<td>out</td>
<td>IOL37[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">SWDIO</td>
<td></td>
<td>AB1/5</td>
<td>Y</td>
<td>io</td>
<td>IOB17[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">SWCLK</td>
<td></td>
<td>AB2/5</td>
<td>Y</td>
<td>io</td>
<td>IOB17[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cmos0_en</td>
<td></td>
<td>AB7/5</td>
<td>Y</td>
<td>io</td>
<td>IOB36[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cmos1_en</td>
<td></td>
<td>V7/5</td>
<td>Y</td>
<td>io</td>
<td>IOB4[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">splicing_en</td>
<td></td>
<td>AA3/5</td>
<td>Y</td>
<td>io</td>
<td>IOB9[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">OUT1</td>
<td></td>
<td>AB6/5</td>
<td>Y</td>
<td>io</td>
<td>IOB27[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">OUT2</td>
<td></td>
<td>AB8/5</td>
<td>Y</td>
<td>io</td>
<td>IOB37[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">OUT3</td>
<td></td>
<td>Y5/5</td>
<td>Y</td>
<td>io</td>
<td>IOB6[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">LED1</td>
<td></td>
<td>U17/3</td>
<td>Y</td>
<td>io</td>
<td>IOR82[B]</td>
<td>LVCMOS15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">LED2</td>
<td></td>
<td>U19/3</td>
<td>Y</td>
<td>io</td>
<td>IOR83[A]</td>
<td>LVCMOS15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">LED3</td>
<td></td>
<td>U18/3</td>
<td>Y</td>
<td>io</td>
<td>IOR83[B]</td>
<td>LVCMOS15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">cam0_sda</td>
<td></td>
<td>W17/4</td>
<td>Y</td>
<td>io</td>
<td>IOB87[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cam1_sda</td>
<td></td>
<td>C22/2</td>
<td>Y</td>
<td>io</td>
<td>IOR18[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">IO_ddr_dq[0]</td>
<td></td>
<td>M5/6</td>
<td>Y</td>
<td>io</td>
<td>IOL49[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">IO_ddr_dq[1]</td>
<td></td>
<td>T3/6</td>
<td>Y</td>
<td>io</td>
<td>IOL56[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">IO_ddr_dq[2]</td>
<td></td>
<td>M4/6</td>
<td>Y</td>
<td>io</td>
<td>IOL46[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">IO_ddr_dq[3]</td>
<td></td>
<td>T2/6</td>
<td>Y</td>
<td>io</td>
<td>IOL50[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">IO_ddr_dq[4]</td>
<td></td>
<td>Y1/6</td>
<td>Y</td>
<td>io</td>
<td>IOL55[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">IO_ddr_dq[5]</td>
<td></td>
<td>U1/6</td>
<td>Y</td>
<td>io</td>
<td>IOL47[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">IO_ddr_dq[6]</td>
<td></td>
<td>N4/6</td>
<td>Y</td>
<td>io</td>
<td>IOL48[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">IO_ddr_dq[7]</td>
<td></td>
<td>V1/6</td>
<td>Y</td>
<td>io</td>
<td>IOL51[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">IO_ddr_dq[8]</td>
<td></td>
<td>R1/7</td>
<td>Y</td>
<td>io</td>
<td>IOL44[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">IO_ddr_dq[9]</td>
<td></td>
<td>K3/7</td>
<td>Y</td>
<td>io</td>
<td>IOL35[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">IO_ddr_dq[10]</td>
<td></td>
<td>P1/7</td>
<td>Y</td>
<td>io</td>
<td>IOL43[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">IO_ddr_dq[11]</td>
<td></td>
<td>J1/7</td>
<td>Y</td>
<td>io</td>
<td>IOL32[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">IO_ddr_dq[12]</td>
<td></td>
<td>K5/7</td>
<td>Y</td>
<td>io</td>
<td>IOL33[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">IO_ddr_dq[13]</td>
<td></td>
<td>H3/7</td>
<td>Y</td>
<td>io</td>
<td>IOL28[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">IO_ddr_dq[14]</td>
<td></td>
<td>M2/7</td>
<td>Y</td>
<td>io</td>
<td>IOL42[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">IO_ddr_dq[15]</td>
<td></td>
<td>H2/7</td>
<td>Y</td>
<td>io</td>
<td>IOL29[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">IO_ddr_dqs[0]</td>
<td>IO_ddr_dqs_n[0]</td>
<td>P4,R4/6</td>
<td>Y</td>
<td>io</td>
<td>IOL53</td>
<td>SSTL15D</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<tr>
<td class="label">IO_ddr_dqs[1]</td>
<td>IO_ddr_dqs_n[1]</td>
<td>L2,L1/7</td>
<td>Y</td>
<td>io</td>
<td>IOL34</td>
<td>SSTL15D</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
</table>
<br/>
<h2><a name="All_Package_Pins">All Package Pins:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Loc./Bank</b></td>
<td><b>Signal</b></td>
<td><b>Dir.</b></td>
<td><b>Site</b></td>
<td><b>IO Type</b></td>
<td><b>Drive</b></td>
<td><b>Pull Mode</b></td>
<td><b>PCI Clamp</b></td>
<td><b>Hysteresis</b></td>
<td><b>Open Drain</b></td>
<td><b>Slew Rate</b></td>
<td><b>Vref</b></td>
<td><b>Single Resistor</b></td>
<td><b>Diff Resistor</b></td>
<td><b>Bank Vccio</b></td>
</tr>
<td class="label">D5/0</td>
<td>-</td>
<td>in</td>
<td>IOT2[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">D6/0</td>
<td>-</td>
<td>in</td>
<td>IOT2[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">E6/0</td>
<td>-</td>
<td>in</td>
<td>IOT3[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">E7/0</td>
<td>-</td>
<td>in</td>
<td>IOT3[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">D4/0</td>
<td>-</td>
<td>in</td>
<td>IOT4[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">C4/0</td>
<td>-</td>
<td>in</td>
<td>IOT4[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">F6/0</td>
<td>-</td>
<td>in</td>
<td>IOT6[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">F7/0</td>
<td>-</td>
<td>in</td>
<td>IOT6[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">C5/0</td>
<td>-</td>
<td>in</td>
<td>IOT7[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">C6/0</td>
<td>-</td>
<td>in</td>
<td>IOT7[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">B1/0</td>
<td>-</td>
<td>in</td>
<td>IOT9[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">A1/0</td>
<td>-</td>
<td>in</td>
<td>IOT9[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">D7/0</td>
<td>-</td>
<td>in</td>
<td>IOT17[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">D8/0</td>
<td>-</td>
<td>in</td>
<td>IOT17[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">A2/0</td>
<td>O_tmds_clk_p</td>
<td>out</td>
<td>IOT18[A]</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">A3/0</td>
<td>O_tmds_clk_n</td>
<td>out</td>
<td>IOT18[B]</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">C7/0</td>
<td>-</td>
<td>in</td>
<td>IOT20[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">C8/0</td>
<td>-</td>
<td>in</td>
<td>IOT20[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">A4/0</td>
<td>-</td>
<td>in</td>
<td>IOT21[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">A5/0</td>
<td>-</td>
<td>in</td>
<td>IOT21[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">B6/0</td>
<td>O_tmds_data_p[0]</td>
<td>out</td>
<td>IOT24[A]</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">A6/0</td>
<td>O_tmds_data_n[0]</td>
<td>out</td>
<td>IOT24[B]</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">E8/0</td>
<td>-</td>
<td>in</td>
<td>IOT25[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">E9/0</td>
<td>-</td>
<td>in</td>
<td>IOT25[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">B7/0</td>
<td>-</td>
<td>in</td>
<td>IOT27[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">A7/0</td>
<td>-</td>
<td>in</td>
<td>IOT27[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">D9/0</td>
<td>-</td>
<td>in</td>
<td>IOT30[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">D10/0</td>
<td>-</td>
<td>in</td>
<td>IOT30[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">C9/0</td>
<td>-</td>
<td>in</td>
<td>IOT36[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">C10/0</td>
<td>-</td>
<td>in</td>
<td>IOT36[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">B8/0</td>
<td>-</td>
<td>in</td>
<td>IOT37[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">A8/0</td>
<td>-</td>
<td>in</td>
<td>IOT37[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">A9/0</td>
<td>O_tmds_data_p[1]</td>
<td>out</td>
<td>IOT40[A]</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">A10/0</td>
<td>O_tmds_data_n[1]</td>
<td>out</td>
<td>IOT40[B]</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">E10/0</td>
<td>-</td>
<td>in</td>
<td>IOT41[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">E11/0</td>
<td>-</td>
<td>in</td>
<td>IOT41[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">A11/0</td>
<td>O_tmds_data_p[2]</td>
<td>out</td>
<td>IOT42[A]</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">A12/0</td>
<td>O_tmds_data_n[2]</td>
<td>out</td>
<td>IOT42[B]</td>
<td>LVDS25</td>
<td>3.5</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">B11/0</td>
<td>-</td>
<td>in</td>
<td>IOT45[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">B12/0</td>
<td>-</td>
<td>in</td>
<td>IOT45[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>2.5</td>
</tr>
<td class="label">D11/1</td>
<td>-</td>
<td>in</td>
<td>IOT48[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">D12/1</td>
<td>-</td>
<td>in</td>
<td>IOT48[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">C11/1</td>
<td>-</td>
<td>in</td>
<td>IOT51[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">C12/1</td>
<td>-</td>
<td>in</td>
<td>IOT51[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">E12/1</td>
<td>-</td>
<td>in</td>
<td>IOT52[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">E13/1</td>
<td>-</td>
<td>in</td>
<td>IOT52[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">A13/1</td>
<td>-</td>
<td>in</td>
<td>IOT53[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">A14/1</td>
<td>-</td>
<td>in</td>
<td>IOT53[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">A15/1</td>
<td>-</td>
<td>in</td>
<td>IOT56[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">B15/1</td>
<td>-</td>
<td>in</td>
<td>IOT56[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">C13/1</td>
<td>-</td>
<td>in</td>
<td>IOT57[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">D13/1</td>
<td>-</td>
<td>in</td>
<td>IOT57[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">A16/1</td>
<td>-</td>
<td>in</td>
<td>IOT63[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">B16/1</td>
<td>-</td>
<td>in</td>
<td>IOT63[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">C14/1</td>
<td>-</td>
<td>in</td>
<td>IOT66[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">C15/1</td>
<td>-</td>
<td>in</td>
<td>IOT66[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">A17/1</td>
<td>-</td>
<td>in</td>
<td>IOT68[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">B17/1</td>
<td>-</td>
<td>in</td>
<td>IOT68[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">D14/1</td>
<td>-</td>
<td>in</td>
<td>IOT69[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">D15/1</td>
<td>-</td>
<td>in</td>
<td>IOT69[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">A18/1</td>
<td>-</td>
<td>in</td>
<td>IOT72[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">A19/1</td>
<td>-</td>
<td>in</td>
<td>IOT72[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">C16/1</td>
<td>-</td>
<td>in</td>
<td>IOT73[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">C17/1</td>
<td>-</td>
<td>in</td>
<td>IOT73[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">A20/1</td>
<td>-</td>
<td>in</td>
<td>IOT75[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">A21/1</td>
<td>-</td>
<td>in</td>
<td>IOT75[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">C18/1</td>
<td>-</td>
<td>in</td>
<td>IOT76[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">C19/1</td>
<td>-</td>
<td>in</td>
<td>IOT76[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">D16/1</td>
<td>-</td>
<td>in</td>
<td>IOT84[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">E16/1</td>
<td>-</td>
<td>in</td>
<td>IOT84[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">E14/1</td>
<td>-</td>
<td>in</td>
<td>IOT86[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">E15/1</td>
<td>-</td>
<td>in</td>
<td>IOT86[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">D17/1</td>
<td>-</td>
<td>in</td>
<td>IOT87[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">D18/1</td>
<td>-</td>
<td>in</td>
<td>IOT87[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">F16/1</td>
<td>-</td>
<td>in</td>
<td>IOT89[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">F17/1</td>
<td>-</td>
<td>in</td>
<td>IOT89[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">A22/1</td>
<td>-</td>
<td>in</td>
<td>IOT90[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">B22/1</td>
<td>-</td>
<td>in</td>
<td>IOT90[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">E17/1</td>
<td>-</td>
<td>in</td>
<td>IOT91[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">E18/1</td>
<td>-</td>
<td>in</td>
<td>IOT91[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>-</td>
</tr>
<td class="label">U6/5</td>
<td>-</td>
<td>in</td>
<td>IOB2[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">U7/5</td>
<td>-</td>
<td>in</td>
<td>IOB2[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">W5/5</td>
<td>-</td>
<td>in</td>
<td>IOB3[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">W6/5</td>
<td>-</td>
<td>in</td>
<td>IOB3[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">V6/5</td>
<td>-</td>
<td>in</td>
<td>IOB4[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">V7/5</td>
<td>cmos1_en</td>
<td>in</td>
<td>IOB4[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">Y4/5</td>
<td>-</td>
<td>in</td>
<td>IOB6[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">Y5/5</td>
<td>OUT3</td>
<td>io</td>
<td>IOB6[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">V8/5</td>
<td>-</td>
<td>in</td>
<td>IOB7[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">V9/5</td>
<td>-</td>
<td>in</td>
<td>IOB7[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">Y3/5</td>
<td>-</td>
<td>in</td>
<td>IOB9[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AA3/5</td>
<td>splicing_en</td>
<td>in</td>
<td>IOB9[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB1/5</td>
<td>SWDIO</td>
<td>io</td>
<td>IOB17[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB2/5</td>
<td>SWCLK</td>
<td>in</td>
<td>IOB17[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">Y6/5</td>
<td>-</td>
<td>in</td>
<td>IOB18[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AA6/5</td>
<td>-</td>
<td>in</td>
<td>IOB18[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">W7/5</td>
<td>-</td>
<td>in</td>
<td>IOB20[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">W8/5</td>
<td>-</td>
<td>in</td>
<td>IOB20[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB3/5</td>
<td>sys_rst_n</td>
<td>in</td>
<td>IOB21[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB4/5</td>
<td>-</td>
<td>in</td>
<td>IOB21[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">Y7/5</td>
<td>-</td>
<td>in</td>
<td>IOB24[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">Y8/5</td>
<td>-</td>
<td>in</td>
<td>IOB24[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">V10/5</td>
<td>-</td>
<td>in</td>
<td>IOB25[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">V11/5</td>
<td>-</td>
<td>in</td>
<td>IOB25[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB5/5</td>
<td>-</td>
<td>in</td>
<td>IOB27[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB6/5</td>
<td>OUT1</td>
<td>io</td>
<td>IOB27[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">W9/5</td>
<td>-</td>
<td>in</td>
<td>IOB30[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">Y9/5</td>
<td>-</td>
<td>in</td>
<td>IOB30[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AA7/5</td>
<td>-</td>
<td>in</td>
<td>IOB36[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB7/5</td>
<td>cmos0_en</td>
<td>in</td>
<td>IOB36[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AA8/5</td>
<td>-</td>
<td>in</td>
<td>IOB37[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB8/5</td>
<td>OUT2</td>
<td>io</td>
<td>IOB37[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">W10/5</td>
<td>-</td>
<td>in</td>
<td>IOB40[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">W11/5</td>
<td>-</td>
<td>in</td>
<td>IOB40[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AA11/5</td>
<td>-</td>
<td>in</td>
<td>IOB41[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB11/5</td>
<td>-</td>
<td>in</td>
<td>IOB41[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">Y10/5</td>
<td>-</td>
<td>in</td>
<td>IOB42[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">Y11/5</td>
<td>-</td>
<td>in</td>
<td>IOB42[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB9/5</td>
<td>-</td>
<td>in</td>
<td>IOB45[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB10/5</td>
<td>-</td>
<td>in</td>
<td>IOB45[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB12/4</td>
<td>-</td>
<td>in</td>
<td>IOB48[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AA12/4</td>
<td>-</td>
<td>in</td>
<td>IOB48[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">Y12/4</td>
<td>-</td>
<td>in</td>
<td>IOB51[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">Y13/4</td>
<td>-</td>
<td>in</td>
<td>IOB51[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">W12/4</td>
<td>cam0_vsync</td>
<td>in</td>
<td>IOB52[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">W13/4</td>
<td>cam0_href</td>
<td>in</td>
<td>IOB52[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB13/4</td>
<td>-</td>
<td>in</td>
<td>IOB53[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB14/4</td>
<td>-</td>
<td>in</td>
<td>IOB53[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB15/4</td>
<td>-</td>
<td>in</td>
<td>IOB56[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AA15/4</td>
<td>-</td>
<td>in</td>
<td>IOB56[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">V12/4</td>
<td>-</td>
<td>in</td>
<td>IOB57[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">V13/4</td>
<td>-</td>
<td>in</td>
<td>IOB57[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">Y14/4</td>
<td>-</td>
<td>in</td>
<td>IOB63[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">Y15/4</td>
<td>cam0_data[5]</td>
<td>in</td>
<td>IOB63[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB16/4</td>
<td>-</td>
<td>in</td>
<td>IOB66[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AA16/4</td>
<td>-</td>
<td>in</td>
<td>IOB66[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">V14/4</td>
<td>cam1_rst_n</td>
<td>out</td>
<td>IOB68[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">V15/4</td>
<td>cam1_data[1]</td>
<td>in</td>
<td>IOB68[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB17/4</td>
<td>-</td>
<td>in</td>
<td>IOB69[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB18/4</td>
<td>-</td>
<td>in</td>
<td>IOB69[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AA17/4</td>
<td>cam0_data[2]</td>
<td>in</td>
<td>IOB72[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">Y17/4</td>
<td>cam0_data[1]</td>
<td>in</td>
<td>IOB72[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">W14/4</td>
<td>cam0_pclk</td>
<td>in</td>
<td>IOB73[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">W15/4</td>
<td>cam0_data[0]</td>
<td>in</td>
<td>IOB73[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB19/4</td>
<td>-</td>
<td>in</td>
<td>IOB75[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AB20/4</td>
<td>-</td>
<td>in</td>
<td>IOB75[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">Y16/4</td>
<td>-</td>
<td>in</td>
<td>IOB76[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">W16/4</td>
<td>cam0_data[4]</td>
<td>in</td>
<td>IOB76[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">Y19/4</td>
<td>cam0_data[3]</td>
<td>in</td>
<td>IOB84[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">Y18/4</td>
<td>cam0_scl</td>
<td>out</td>
<td>IOB84[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">V16/4</td>
<td>cam1_data[3]</td>
<td>in</td>
<td>IOB86[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">U16/4</td>
<td>cam1_data[2]</td>
<td>in</td>
<td>IOB86[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">W17/4</td>
<td>cam0_sda</td>
<td>out</td>
<td>IOB87[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">W18/4</td>
<td>-</td>
<td>in</td>
<td>IOB87[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">AA20/4</td>
<td>cam0_data[6]</td>
<td>in</td>
<td>IOB89[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">Y20/4</td>
<td>cam0_data[7]</td>
<td>in</td>
<td>IOB89[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">V17/4</td>
<td>-</td>
<td>in</td>
<td>IOB90[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">V18/4</td>
<td>-</td>
<td>in</td>
<td>IOB90[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">W19/4</td>
<td>cam1_pclk</td>
<td>in</td>
<td>IOB91[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">V19/4</td>
<td>cam1_vsync</td>
<td>in</td>
<td>IOB91[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">E5/7</td>
<td>O_ddr_addr[3]</td>
<td>out</td>
<td>IOL2[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">F5/7</td>
<td>-</td>
<td>in</td>
<td>IOL2[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">B3/7</td>
<td>O_ddr_odt</td>
<td>out</td>
<td>IOL3[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">B2/7</td>
<td>-</td>
<td>in</td>
<td>IOL3[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">G6/7</td>
<td>O_ddr_addr[2]</td>
<td>out</td>
<td>IOL5[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">G5/7</td>
<td>-</td>
<td>in</td>
<td>IOL5[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">D3/7</td>
<td>O_ddr_cas_n</td>
<td>out</td>
<td>IOL7[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">C3/7</td>
<td>-</td>
<td>in</td>
<td>IOL7[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">E4/7</td>
<td>O_ddr_cke</td>
<td>out</td>
<td>IOL8[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">E3/7</td>
<td>-</td>
<td>in</td>
<td>IOL8[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">F4/7</td>
<td>O_ddr_ba[0]</td>
<td>out</td>
<td>IOL9[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">G4/7</td>
<td>-</td>
<td>in</td>
<td>IOL9[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">F3/7</td>
<td>O_ddr_ba[2]</td>
<td>out</td>
<td>IOL11[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">G3/7</td>
<td>-</td>
<td>in</td>
<td>IOL11[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">H5/7</td>
<td>O_ddr_addr[7]</td>
<td>out</td>
<td>IOL14[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">J5/7</td>
<td>-</td>
<td>in</td>
<td>IOL14[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">C2/7</td>
<td>O_ddr_we_n</td>
<td>out</td>
<td>IOL15[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">C1/7</td>
<td>-</td>
<td>in</td>
<td>IOL15[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">D1/7</td>
<td>O_ddr_ras_n</td>
<td>out</td>
<td>IOL16[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">E1/7</td>
<td>-</td>
<td>in</td>
<td>IOL16[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">F2/7</td>
<td>O_ddr_addr[5]</td>
<td>out</td>
<td>IOL18[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">G2/7</td>
<td>-</td>
<td>in</td>
<td>IOL18[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">F1/7</td>
<td>O_ddr_addr[0]</td>
<td>out</td>
<td>IOL20[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">G1/7</td>
<td>-</td>
<td>in</td>
<td>IOL20[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">H4/7</td>
<td>O_ddr_addr[9]</td>
<td>out</td>
<td>IOL21[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">J4/7</td>
<td>-</td>
<td>in</td>
<td>IOL21[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">H3/7</td>
<td>IO_ddr_dq[13]</td>
<td>io</td>
<td>IOL28[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">J3/7</td>
<td>-</td>
<td>in</td>
<td>IOL28[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">H2/7</td>
<td>IO_ddr_dq[15]</td>
<td>io</td>
<td>IOL29[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">H1/7</td>
<td>-</td>
<td>in</td>
<td>IOL29[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">J1/7</td>
<td>IO_ddr_dq[11]</td>
<td>io</td>
<td>IOL32[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">K1/7</td>
<td>-</td>
<td>in</td>
<td>IOL32[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">K5/7</td>
<td>IO_ddr_dq[12]</td>
<td>io</td>
<td>IOL33[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">L5/7</td>
<td>-</td>
<td>in</td>
<td>IOL33[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">L2/7</td>
<td>IO_ddr_dqs[1]</td>
<td>io</td>
<td>IOL34[A]</td>
<td>SSTL15D</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">L1/7</td>
<td>IO_ddr_dqs_n[1]</td>
<td>io</td>
<td>IOL34[B]</td>
<td>SSTL15D</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">K3/7</td>
<td>IO_ddr_dq[9]</td>
<td>io</td>
<td>IOL35[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">L3/7</td>
<td>-</td>
<td>in</td>
<td>IOL35[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">K4/7</td>
<td>O_ddr_dqm[1]</td>
<td>out</td>
<td>IOL37[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">L4/7</td>
<td>-</td>
<td>in</td>
<td>IOL37[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">M2/7</td>
<td>IO_ddr_dq[14]</td>
<td>io</td>
<td>IOL42[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">M1/7</td>
<td>-</td>
<td>in</td>
<td>IOL42[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">P1/7</td>
<td>IO_ddr_dq[10]</td>
<td>io</td>
<td>IOL43[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">N1/7</td>
<td>-</td>
<td>in</td>
<td>IOL43[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">R1/7</td>
<td>IO_ddr_dq[8]</td>
<td>io</td>
<td>IOL44[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">T1/7</td>
<td>-</td>
<td>in</td>
<td>IOL44[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">M4/6</td>
<td>IO_ddr_dq[2]</td>
<td>io</td>
<td>IOL46[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">M3/6</td>
<td>-</td>
<td>in</td>
<td>IOL46[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">U1/6</td>
<td>IO_ddr_dq[5]</td>
<td>io</td>
<td>IOL47[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">U2/6</td>
<td>-</td>
<td>in</td>
<td>IOL47[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">N4/6</td>
<td>IO_ddr_dq[6]</td>
<td>io</td>
<td>IOL48[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">N3/6</td>
<td>-</td>
<td>in</td>
<td>IOL48[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">M5/6</td>
<td>IO_ddr_dq[0]</td>
<td>io</td>
<td>IOL49[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">N5/6</td>
<td>-</td>
<td>in</td>
<td>IOL49[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">T2/6</td>
<td>IO_ddr_dq[3]</td>
<td>io</td>
<td>IOL50[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">R2/6</td>
<td>-</td>
<td>in</td>
<td>IOL50[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">V1/6</td>
<td>IO_ddr_dq[7]</td>
<td>io</td>
<td>IOL51[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">W1/6</td>
<td>-</td>
<td>in</td>
<td>IOL51[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">P3/6</td>
<td>O_ddr_dqm[0]</td>
<td>out</td>
<td>IOL52[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">R3/6</td>
<td>-</td>
<td>in</td>
<td>IOL52[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">P4/6</td>
<td>IO_ddr_dqs[0]</td>
<td>io</td>
<td>IOL53[A]</td>
<td>SSTL15D</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">R4/6</td>
<td>IO_ddr_dqs_n[0]</td>
<td>io</td>
<td>IOL53[B]</td>
<td>SSTL15D</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">Y1/6</td>
<td>IO_ddr_dq[4]</td>
<td>io</td>
<td>IOL55[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">Y2/6</td>
<td>-</td>
<td>in</td>
<td>IOL55[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">T3/6</td>
<td>IO_ddr_dq[1]</td>
<td>io</td>
<td>IOL56[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>INTERNAL</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">U3/6</td>
<td>-</td>
<td>in</td>
<td>IOL56[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">V3/6</td>
<td>O_ddr_addr[4]</td>
<td>out</td>
<td>IOL73[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">W3/6</td>
<td>-</td>
<td>in</td>
<td>IOL73[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">AA1/6</td>
<td>O_ddr_addr[13]</td>
<td>out</td>
<td>IOL74[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">AA2/6</td>
<td>-</td>
<td>in</td>
<td>IOL74[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">P5/6</td>
<td>O_ddr_addr[10]</td>
<td>out</td>
<td>IOL76[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">R5/6</td>
<td>-</td>
<td>in</td>
<td>IOL76[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">T4/6</td>
<td>O_ddr_ba[1]</td>
<td>out</td>
<td>IOL77[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">U4/6</td>
<td>-</td>
<td>in</td>
<td>IOL77[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">V4/6</td>
<td>O_ddr_reset_n</td>
<td>out</td>
<td>IOL79[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">W4/6</td>
<td>-</td>
<td>in</td>
<td>IOL79[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">V5/6</td>
<td>O_ddr_addr[1]</td>
<td>out</td>
<td>IOL82[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">U5/6</td>
<td>-</td>
<td>in</td>
<td>IOL82[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">T5/6</td>
<td>O_ddr_addr[12]</td>
<td>out</td>
<td>IOL83[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">T6/6</td>
<td>-</td>
<td>in</td>
<td>IOL83[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">F18/2</td>
<td>-</td>
<td>in</td>
<td>IOR2[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">F19/2</td>
<td>-</td>
<td>in</td>
<td>IOR2[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">E19/2</td>
<td>-</td>
<td>in</td>
<td>IOR3[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">E20/2</td>
<td>-</td>
<td>in</td>
<td>IOR3[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">G17/2</td>
<td>-</td>
<td>in</td>
<td>IOR5[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">G18/2</td>
<td>-</td>
<td>in</td>
<td>IOR5[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">H19/2</td>
<td>-</td>
<td>in</td>
<td>IOR7[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">H18/2</td>
<td>-</td>
<td>in</td>
<td>IOR7[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">D19/2</td>
<td>-</td>
<td>in</td>
<td>IOR8[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">D20/2</td>
<td>-</td>
<td>in</td>
<td>IOR8[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">B20/2</td>
<td>-</td>
<td>in</td>
<td>IOR9[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">C20/2</td>
<td>-</td>
<td>in</td>
<td>IOR9[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">B21/2</td>
<td>-</td>
<td>in</td>
<td>IOR11[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">C21/2</td>
<td>-</td>
<td>in</td>
<td>IOR11[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">J18/2</td>
<td>-</td>
<td>in</td>
<td>IOR14[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">K18/2</td>
<td>-</td>
<td>in</td>
<td>IOR14[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">G19/2</td>
<td>-</td>
<td>in</td>
<td>IOR15[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">G20/2</td>
<td>-</td>
<td>in</td>
<td>IOR15[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">F20/2</td>
<td>-</td>
<td>in</td>
<td>IOR16[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">F21/2</td>
<td>-</td>
<td>in</td>
<td>IOR16[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">C22/2</td>
<td>cam1_sda</td>
<td>out</td>
<td>IOR18[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">D22/2</td>
<td>cam1_data[7]</td>
<td>in</td>
<td>IOR18[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">H20/2</td>
<td>-</td>
<td>in</td>
<td>IOR20[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">H21/2</td>
<td>-</td>
<td>in</td>
<td>IOR20[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">J19/2</td>
<td>-</td>
<td>in</td>
<td>IOR21[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">J20/2</td>
<td>-</td>
<td>in</td>
<td>IOR21[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">F22/2</td>
<td>cam1_scl</td>
<td>out</td>
<td>IOR28[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">E22/2</td>
<td>cam1_data[4]</td>
<td>in</td>
<td>IOR28[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">G21/2</td>
<td>cam1_data[5]</td>
<td>in</td>
<td>IOR29[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">G22/2</td>
<td>cam1_data[0]</td>
<td>in</td>
<td>IOR29[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">H22/2</td>
<td>cam1_href</td>
<td>in</td>
<td>IOR32[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">J22/2</td>
<td>cam1_data[6]</td>
<td>in</td>
<td>IOR32[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">K22/2</td>
<td>-</td>
<td>in</td>
<td>IOR33[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">L22/2</td>
<td>-</td>
<td>in</td>
<td>IOR33[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">K19/2</td>
<td>-</td>
<td>in</td>
<td>IOR34[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">L19/2</td>
<td>cam0_rst_n</td>
<td>out</td>
<td>IOR34[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">K20/2</td>
<td>UART0TXD_o</td>
<td>out</td>
<td>IOR35[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">L20/2</td>
<td>UART0RXD_i</td>
<td>in</td>
<td>IOR35[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">L21/2</td>
<td>-</td>
<td>in</td>
<td>IOR37[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">M21/2</td>
<td>-</td>
<td>in</td>
<td>IOR37[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">M22/2</td>
<td>-</td>
<td>out</td>
<td>IOR42[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">N22/2</td>
<td>-</td>
<td>in</td>
<td>IOR42[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">N20/2</td>
<td>-</td>
<td>in</td>
<td>IOR43[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">M20/2</td>
<td>-</td>
<td>in</td>
<td>IOR43[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">M19/2</td>
<td>sys_clk</td>
<td>in</td>
<td>IOR44[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">N19/2</td>
<td>-</td>
<td>in</td>
<td>IOR44[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<td class="label">P22/3</td>
<td>O_ddr_clk</td>
<td>out</td>
<td>IOR46[A]</td>
<td>SSTL15D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">R22/3</td>
<td>O_ddr_clk_n</td>
<td>out</td>
<td>IOR46[B]</td>
<td>SSTL15D</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">T22/3</td>
<td>-</td>
<td>in</td>
<td>IOR47[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">U22/3</td>
<td>-</td>
<td>in</td>
<td>IOR47[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">U21/3</td>
<td>-</td>
<td>in</td>
<td>IOR48[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">T21/3</td>
<td>-</td>
<td>in</td>
<td>IOR48[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">L18/3</td>
<td>-</td>
<td>in</td>
<td>IOR49[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">M18/3</td>
<td>-</td>
<td>in</td>
<td>IOR49[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">P19/3</td>
<td>-</td>
<td>in</td>
<td>IOR50[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">P20/3</td>
<td>-</td>
<td>in</td>
<td>IOR50[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">N18/3</td>
<td>-</td>
<td>in</td>
<td>IOR51[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">P18/3</td>
<td>-</td>
<td>in</td>
<td>IOR51[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">R20/3</td>
<td>-</td>
<td>in</td>
<td>IOR52[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">R21/3</td>
<td>-</td>
<td>in</td>
<td>IOR52[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">V22/3</td>
<td>-</td>
<td>in</td>
<td>IOR53[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">W22/3</td>
<td>-</td>
<td>in</td>
<td>IOR53[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">T20/3</td>
<td>-</td>
<td>in</td>
<td>IOR55[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">U20/3</td>
<td>-</td>
<td>in</td>
<td>IOR55[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">T19/3</td>
<td>-</td>
<td>in</td>
<td>IOR56[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">R19/3</td>
<td>-</td>
<td>in</td>
<td>IOR56[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">Y22/3</td>
<td>O_ddr_addr[6]</td>
<td>out</td>
<td>IOR73[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">AA22/3</td>
<td>-</td>
<td>in</td>
<td>IOR73[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">R18/3</td>
<td>-</td>
<td>in</td>
<td>IOR74[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">T18/3</td>
<td>-</td>
<td>in</td>
<td>IOR74[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">Y21/3</td>
<td>O_ddr_addr[11]</td>
<td>out</td>
<td>IOR76[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">AA21/3</td>
<td>-</td>
<td>in</td>
<td>IOR76[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">W20/3</td>
<td>O_ddr_cs_n</td>
<td>out</td>
<td>IOR77[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">V20/3</td>
<td>-</td>
<td>in</td>
<td>IOR77[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">AB22/3</td>
<td>O_ddr_addr[8]</td>
<td>out</td>
<td>IOR79[A]</td>
<td>SSTL15</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">AB21/3</td>
<td>-</td>
<td>in</td>
<td>IOR79[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">T17/3</td>
<td>-</td>
<td>in</td>
<td>IOR82[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">U17/3</td>
<td>LED1</td>
<td>io</td>
<td>IOR82[B]</td>
<td>LVCMOS15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">U19/3</td>
<td>LED2</td>
<td>io</td>
<td>IOR83[A]</td>
<td>LVCMOS15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
<td class="label">U18/3</td>
<td>LED3</td>
<td>io</td>
<td>IOR83[B]</td>
<td>LVCMOS15</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>OFF</td>
<td>FAST</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.5</td>
</tr>
</table>
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